Conventionally, the input and output connections to MOS integrated circuits must be protected from electrostatic discharge (ESD) voltages as may occur in the ordinary handling of an MOS integrated device or as a consequence of the environment in which the device is operated. This sensitivity to ESD voltages is generally due to the thinness of the MOS transistor gate oxide layer as a desired necessity for fast MOS transistors. Typically, a conventional MOS transistor will have a gate oxide thickness of approximately 600 Angstroms, resulting in an oxide breakdown voltage of approximately 50 to 60 volts. However, ESD voltages may easily reach several hundred volts. Although current limited, ESD voltages substantially greater than the gate oxide breakdown voltage will severely degrade, if not destroy the affected MOS transistors.
A simple ESD diode network can be utilized to clamp input and output voltages to the voltage supply rails of the integrated circuit. Thus, any over-voltage or under-voltage is shunted through a forward biased diode to a corresponding supply rail.
A limitation in the use of such ESD diode networks is that the diodes themselves may be damaged by the current associated with very high ESD voltages. A resistor is therefore often used as a current limiter. Typically, a low resistive value is placed between the bonding pad, in turn connected to the external contact of the integrated circuit, and the remainder of the integrated circuit generally including the ESD protection diode network. Only a small resistive value of on the order of 100 to 1 K: is necessary to provide the required current limiting to protect the diode network. Indeed, a low value is generally desired to minimally impact the speed of the integrated circuit as a whole.
A distinctive problem of even such modified ESD diode networks is that some conventional MOS integrated circuits are expected to operate normally with input and output voltages that are significantly outside of the voltage range defined by the integrated circuit's voltage supply rail potentials. Operation of such integrated circuits, if not simply precluded, may be significantly compromised by effects secondary to the operation of the ESD diode network. For example, an externally sustained or periodic input or output voltage only a few volts above the integrated circuit's positive voltage supply rail potential, though otherwise acceptable, will result in a substantial current being shunted by a protection network diode to the positive supply voltage rail. Not only does this result in the creation of substantial voltage supply noise directly on-chip with the integrated circuit, but this may result in substantial asymmetric or surge heating of the integrated circuit. If instead the externally sustained voltage potential is several volts below the negative voltage supply rail potential, a false ground or reference voltage condition may arise in addition to any associated noise and heating problems. Consequently, the operational accuracy of the integrated circuit may be compromised.
In any case, the substantial current passed by the ESD protection diode network may invoke the operation of a parasitic transistor inherently present as a consequence of integrated circuit monolithic fabrication. The uncontrolled operation of a parasitic transistor will, in turn, force the integrated circuit into a latched-up or completely inoperative state that, if not destructive, requires all power to be removed from the integrated circuit before proper operation is restored.
An alternate approach to ESD voltage protection is to utilize an active circuit network. However, the required circuit complexity, power consumption entailed and usage of integrated circuit surface area as necessary for an active circuit network sufficient to provide ESD voltage protection will generally outweigh the benefits that might be had over using a simple ESD diode network. Consequently, the use of active ESD integrated circuit voltage protection circuits is generally not preferred.